In my design I have 4 incoming slave interfaces, each with AXI ID widths of 4 bits going to an Interconnect from an upstream interconnect.
However, the master interface has an ID width of 4 instead of 6 as expected.
Is this an issue?
The example above is incorrect tool behavior.
The ID_WIDTH of the AXI Interface should be 6, assuming that ID-width decreasing features like data-width conversion, Minimize Area (SASD) strategy, or AXI4-Lite protocol conversion are accounted for.
Incorrect ID width can result in functional issues.
To work around this issue, consider increasing the maximum ID width of the incoming master, this often results in a correct ID width.
Using individual AXI Crossbar components can be another temporary workaround.
This issue is planned to be fixed starting in Vivado 2015.1.