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AR# 63019

Vivado Power Analysis - How do I set clocking specifications (create_clock or create_generated_clock for all clocks)?


How do I set clocking specifications (create_clock or create_generated_clock for all clocks)?


Design Clocks are the main source of Dynamic Power estimation.

If no clocks are defined, switching activity estimates will be inaccurate resulting in inaccurate power estimates.

A clock node is identified from Timing constraints which are defined using "create_clock" or "create_generated_clock" XDC commands.

***RECOMMENDATION*** All the required clocks in the design must be defined using "create_clock" OR "create_generated_clock"

The Report Power GUI settings display, reports the clocks defined in the design. 

Make sure that it identifies all of the clocks with the expected requirements.

Once Report Power runs, the Power Report confirms the percentage of clocks defined in the design under 'Summary' View.

This guides user to ensure HIGH confidence level on Clock Activities.
In Tcl mode, use "get_clocks" and "report_clocks" commands to get the list of defined clocks.

Note: Refer to (UG907) Power Analysis & Optimization for more information about Tcl command usage and signal rate or toggle rate usage.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
63015 Vivado Power Analysis - How do I get the most accurate results from report_power? N/A N/A
AR# 63019
Date 12/04/2014
Status Active
Type General Article
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
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