AR# 63022


UltraScale DDR4/DDR3 - Designs targeting dual rank DIMMs with address mirroring fail in hardware


Version Found: DDR4 v6.1, DDR3 v6.1

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

Dual Rank DIMMs that use address mirroring require specific RTL within the MIG IP to support the address mirror between ranks.

While MIG generates designs for dual rank DIMMs that use address mirroring, the RTL is not modified to support the mirroring and as a result the addressing is incorrect.

This will cause hardware failures.


Until this is resolved, If you are targeting dual rank DIMMs using address mirroring in hardware, please open a Service Request for assistance.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69036 UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues N/A N/A
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 63022
Date 01/02/2018
Status Active
Type General Article
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