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AR# 63023

2014.4 Vivado Place - Place DRC fails with CASC-31 error related to cascaded BRAM


My design fails with the following DRC error during placement.

What is this placement restriction and why does it occur?

What are my options to correct this?

CASC-31#1 Error 
Cascade crosses rbrk   
The RAMB36E2 cell core/p0_pipeline/page_buffer/gen_sync_buf_out_fifo[2].sync_buf_out/sync_buf_out_slice1/generate_fifos[0].fifo_synth_sync/blockr.fifo_ram/ram_block_gen1[0].mem_reg_bram_0__6 is cascaded in series to expand the RAMB depth. The cascade connection crosses a Clock region, so the core/p0_pipeline/page_buffer/gen_sync_buf_out_fifo[2].sync_buf_out/sync_buf_out_slice1/generate_fifos[0].fifo_synth_sync/blockr.fifo_ram/ram_block_gen1[0].mem_reg_bram_0__6/CASOREGIMUXB pin should be connected to GND (rather than an active signal: core/p0_pipeline/page_buffer/gen_sync_buf_out_fifo[2].sync_buf_out/sync_buf_out_slice1/generate_fifos[0].fifo_synth_sync/blockr.fifo_ram/n_15_ram_block_gen1[0].mem_reg_bram_0__6_i_1__4). 
Related violations: <none> 


This error occurs when a cascaded BRAM configuration straddles a clock region boundary so that not all BRAMs in the cascade are in the same clock region.

The reason for this restriction has to do with timing.

The solution has to do with the size of the BRAM cascade.

If the cascade is taller than a clock region, then no legal placement is possible and the solution is to limit the size of the cascade at synthesis.

If the cascade is not too large for one clock region then the issue is with placement.

A case has been seen where the placer did not correctly place a cascade in a single clock region.

This case has been fixed for Vivado 2015.1 which is due for release in April.

Meanwhile a work-around is to assign the BRAM cells involved to a pblock and constrain the pblock to an appropriate clock region.

For example use the  Synthesis parameter to limit cascade length to 8:
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter maxBramCascChainLength 8"

Values used should be a power of two.

Use the following Synthesis parameter to disable BRAM cascades:
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter v8SupportBramCascade false"
AR# 63023
Date 12/04/2014
Status Active
Type General Article
  • Virtex UltraScale
  • Vivado Design Suite - 2014.1
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.4
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