We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63025

Design Advisory for Zynq-7000 AP SoC, I2C - I2C Transaction Corruption In Slave Receiver Mode


When the PS I2C controller is in slave receiver mode and more than one I2C slave is connected to the same bus, the PS I2C controller can receive and acknowledge data sent to a different I2C slave if the transferred data pattern contains 0xF0 or 0xF1 followed by the slave address of the PS I2C controller.

For data bytes that follow the slave address, the PS I2C controller sets the i2c.Status_reg0[RXDV] register field to 1 and generates an ACK.

If the intended I2C slave does not acknowledge the data, then the bus becomes corrupted because the I2C master sees an erroneous ACK instead of the NACK from the intended I2C slave.



  1. In the master software application, split messages targeting other slaves into multiple transactions so that the pattern 0xF0 or 0xF1 followed by the Zynq slave address does not appear in the same transaction.

  2. In the master software application, write a SYNC pattern targeting the Zynq slave before transferring the data to other slaves.
    The Zynq I2C controller will change its mode to master receiver after detecting the SYNC word and continuously monitor the bus-active state by polling i2c.Status_reg0 [BA] bit.
    If the I2C master has to transfer to the Zynq slave, it will keep the bus idle for a definite time-period and Zynq I2C controllers software will wait until the timeout period to see if the bus is idle before changing to slave-receiver mode.
    I2C master continues transferring data to Zynq slave.

  3. When both I2C master and slave are implemented in Zynq and there is only one I2C master connected to the same bus, the master software can quiescence the Zynq slave by holding the Zynq slave in reset (write slcr.I2C_RST_CTRL[I2Cx_CPU1X_RST]=1) while transferring data to another slave.
    The Zynq slave controller is brought out of reset before the master controller transfers data to the Zynq slave using a software level handshaking mechanism.
  4. Use an I2C multiplexer chip to isolate the Zynq slave from other slaves on the bus.
    The non-Zynq slaves can be connected to a single I2C bus and the multiplexer can enable one connection at a time between the I2C master and the Zynq slave or the I2C master and other slaves on the bus.
    The I2C master software first selects the slave it wants the data to be transferred to by writing to the I2C multiplexer chip followed by the actual data to be transferred.
  5. Use a soft IP in PL instead of the PS I2C controller.
Device Revision(s) Affected:

Refer to (Xilinx Answer 47916) - Zynq-7000 AP SoC Silicon Revision Differences

Configurations Affected:
All Zynq devices using the PS I2C controller in a multi-slave topology.
This is a third-party errata, this issue will not be fixed.  
AR# 63025
Date 01/28/2015
Status Active
Type Design Advisory
  • Zynq-7000
  • XA Zynq-7000
  • Zynq-7000Q