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AR# 63090

Xapp585 - How to use Xapp585 in Vivado


The current version of Xapp585 is available with a UCF file only.

How can I use Xapp585 in Vivado?


The VHDL and Verilog files do not require any changes. 

It is only the constraints file (UCF) that needs to be updated to an XDC file.

The IOSTANDARD, LOC and DIFF_TERM constraints should be written according to the users pinout. 

This can be done in the Vivado I/O Pin Planning GUI. 

The clock constraint needs to be added to the XDC file, for example:

create_clock -add -name clkin1_p -period 5.833 [get_ports clkin1_p]

The other constraints in the Xapp585 UCF file that need to be ported to the XDC file are the TIG constraints.

These are used to ignore retiming paths from pixel clock to clk_d4 through the gearbox.

For example:

set_false_path -from [get_pins -hier -filter {name =~ *gb0*ram_inst*}]  -to [get_pins -hier -filter {name =~ *gb0*dataout*/D}]
set_false_path -to [get_pins -hier -filter {name =~ *rx*dom_ch*/D}]
set_false_path -to [get_pins -hier -filter {name =~ *rx*dom_ch*/PRE}]
set_false_path -from [get_ports clkin1_p] -to [get_pins -hier -filter {name =~ *rx*iserdes_c?/DDLY}]


Associated Attachments

Name File Size File Type
top5x2_7to1_ddr_rx.xdc 8 KB XDC
top5x2_7to1_ddr_tx.xdc 6 KB XDC
top5x2_7to1_sdr_rx.xdc 8 KB XDC
top5x2_7to1_sdr_tx.xdc 6 KB XDC
AR# 63090
Date 02/09/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
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