We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63147

2014.4 XPE - When increasing the fan out of the clock network it appears that the VCCINT power saturates before reaching the Max number of flip-flops.


In the example below the fan out in the clock tab is incremented in 5K intervals.

In the Virtex-7 690T there are 886,400 registers but is can be seen that the curve saturates before reaching this.

Why does this occur?



This is expected behavior.

This occurs because the clock network will reach a saturation before all of the available flip flops are used.

For example if your design is using 70% of the flip-flops and XPE is not aware of the placement, it will assume that all of the major clock paths are enabled.

If you start to add additional flip flops, this only requires a small clock net to be enabled and these consume much less power.

As a result, the XPE result appears to flatten out towards the higher utilization numbers.

AR# 63147
Date 02/27/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Vivado Design Suite - 2014.4
Page Bookmarked