Description

Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)

Opt_design adds a BUFG between the PLL output clock "freq_refclk" and the FREQREFCLK input to the PHASER_IN in the PHY. 

This can cause minimum pulse width violations in the MIG design.

Solution

It can be seen in the implementation log files that the "retarget" phase in "opt_design" has added this BUFG to the PLL output:

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 10 inverter(s) to 78 load pin(s).
INFO: [Opt 31-194] Inserted BUFG ClkFreq_BUFG_inst to drive 22 load(s) on clock net ClkFreq
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
INFO: [Opt 31-49] Retargeted 0 cell(s).

This extra BUFG is not required and should be removed. 

The issue can be worked around with the following options:

set_param logicopt.enableBUFGinsertCLK 0

(* dont_touch="true" *) wire        freq_refclk;
(* dont_touch="true" *) wire        mem_refclk;
(* dont_touch="true" *) wire        sync_pulse;

Revision History:
1/21/2015 - Initial Release

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