This is a MIG wrapper design targeted on an UltraScale device.
The MIG example design is the Reconfigurable Partition itself, with the top/static being the simple wrapper.
The routing for the first configuration completes successfully and report_route_status flags no error in the netlist.
I run the following command to carve out the Reconfigurable Partition:
update_design -black_box -cell example_top_inst
However, there are routing errors on the two differential clock inputs:
c0_sys_clk_n and c0_sys_clk_p.
This can be found using the report_route_status command.
Nets with Routing Errors:
In this design, the embedded I/O connects to the Reconfigurable Module's port and no PPLOC is assigned as expected.
However, when performing carving, only placed driver/loads are carved away, the routing is still preserved, which causes the routing antenna issue.
This issue is fixed in the 2014.4 release of Vivado.