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AR# 63178

MIG 7 Series - DDR3 - Glitches seen on address/command bus in simulation with 2:1 controller


Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)

When simulating a 2:1 controller, two "X" glitches can be seen on the address and command buses prior to ddr3_reset_n going high. 

The issue is specific to 2:1 mode,  a 4:1 core with similar settings does have this problem.




These glitches cab be safely ignored as they do not violate the DDR3 spec:

Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined).

RESET# needs to be maintained for minimum 200 us with stable power.

Revision History
01/19/2014 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado N/A N/A
AR# 63178
Date 02/03/2015
Status Active
Type Known Issues
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