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AR# 63188

AXI Quad SPI v3.2 - Why are bytes read from the DRR ignored?


Why are bytes read from the DRR ignored?


The reason for this behavior is described on page 54 of (PG153AXI Quad SPI v3.2 Product Guide 

Taking an example:

Command AB is to be issued to the SPI device to read two bytes of data.

This command needs to followed by an address DE and then by two bytes of dummy cycles.

So you would write AB, DE, 00 and 00 to the DTR register.

When this data is transmitted to the SPI device, the DRR FIFO is filled with two dummy bytes corresponding to the command AB, the address DE, and then with the 2 actual bytes of data that are read from the SPI device.

As a result, when reading the DRR FIFO, the first two reads should be ignored.
AR# 63188
Date 01/07/2015
Status Active
Type General Article
  • AXI Quad SPI