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AR# 63212

Ten Gigabit Ethernet MAC - v14.0 Rev.1 - Potential lock up issue with receive AXI-stream FIFO

Description

The 10G MAC example design RX FIFO can enter a state where it is full but data cannot be read out. 

Solution

To work around this issue, remove wr_axis_tvalid from the wr_fifo_full equation below:

Change:

            -- We hold the full signal until the end of frame reception to guarantee that this
            -- frame will be dropped
            elsif (WR_FLOW_CTRL or wr_axis_tlast='1' or wr_axis_tvalid='0') then
               wr_fifo_full            <= '0';


To:

            -- We hold the full signal until the end of frame reception to guarantee that this
            -- frame will be dropped
            elsif (WR_FLOW_CTRL or wr_axis_tlast='1' ) then
               wr_fifo_full            <= '0';


AR# 63212
Date Created 12/19/2014
Last Updated 01/28/2015
Status Active
Type General Article
IP
  • 10 Gigabit Ethernet Media Access Controller