Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)
For DDR3 designs, one MMCM is required for IDELAY reference clock generation.
If memory frequency is > 667 MHz, then the IDELAY reference clock is either 300 MHz or 400 MHz and MIG instantiates extra MMCM.
If I generate the core with the No Buffer option, should I drive a 200Mhz clock to clk_ref_i or can I supply 400Mhz and save one MMCM and some BUFGs?
MIG instantiates an additional MMCM for 300 MHz and 400 MHz reference clock generation, depending on the FPGA speed grade and memory frequency.
Driving 400Mhz on clk_ref_i directly to bypass MMCM require RTL changes which are not supported for OOC flow.
As a result, even with the No Buffer option, you should always drive 200Mhz on clk_ref_.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.