Version Found: MIG v6.1
Version Resolved: See (Xilinx Answer 58435)
Within the MIG UltraScale DDR4/3 PHY Only documentation (PG150 > DDR3/DDR4 > Designing with the Core > Protocol Description > PHY Only Interface), the "rdDataEn" signal is described as follows:
"Read data valid. This signal asserts for one system clock cycle for each completed read operation, indicating that the rdData, rdDataAddr, per_rd_done, and rmw_rd_done signals are valid.
These signals are only valid when rdDataEn asserts. rdData must be consumed when rdDataEn asserts or data is lost. Active-High."
This description should not include "per_rd_done" and "rmw_rd_done" as these will assert separately from rdDataEn.
The proper usage is for custom controllers to exclusively monitor each of the PHY outputs as follows:
The RTL matches this behavior.
The documentation has been updated to match the RTL and behavior noted within this Answer Record in the v7.0 release of (PG150).
01/07/2015 - Initial Release