AR# 63245


Design Advisory for Zynq-7000 SoC, I2C - PS I2C Slave Monitor Mode Can Lock the I2C Bus


The Zynq-7000 I2C Master activated in Slave monitor mode cannot be deactivated by host software when an ACK is not received.

Clearing Control.SLVMON does not terminate the Slave Monitor Mode, leaving the Zynq I2C Master Device in this mode.


The host must set the SLVMON bit in the Control Register to enable the SLAVE MONITOR MODE.

In SLAVE MONITOR MODE, the I2C interface is set as a master.

When a Slave is busy, the host software uses Slave Monitor Mode to wait until the Slave is ready.

It does this by periodically issuing transactions until the slave responds with ACK. (No actual data transfer happens in Slave Monitor Mode).

The master attempts a transfer to a particular slave whenever the host writes to the I2C address register.

If the slave returns NACK when it receives the address, then the master waits for the time interval established by the Slave Monitor Pause register and attempts to address the slave again.

The master continues this cycle until the slave responds with ACK to its address.

When the SLVMON bit is cleared in the Control Register, the Master still attempts a transfer.

The cycle is also supposed to be stopped when host software clears the SLVMON bit.

However, the cycle is not stopped as it should be when SLVMON is cleared.

If the host had set Slave Monitor Mode using an I2C address that does not correspond to any I2C slaves, an ACK will never be received and Slave Monitor Mode will never be exited.



If the Zynq is the only master it cannot communicate with other Slaves on the bus.

In Multi-Master systems this issue may lock the bus and will not allow other master to own the bus.

  1. When the Master Device is receiving NACKs for a long period, then the host should write the address of a Slave Device that exists on the I2C bus and will respond with an ACK to the I2C Address Register.

    This causes the I2C master to use this new address for its next transaction.

    As long as that slave responds with an ACK, Slave Monitor mode will then be exited properly.

  2. Apply a soft reset to the I2C controller when the Controller receives NACK for a long duration and re-configure the controller before commencing for new transfers.

Configurations Affected:
All Zynq-7000 PS I2C controllers operating in slave monitor mode where the bus may not respond with an ACK.
Device Revision(s) Affected:
Refer to (Xilinx Answer 47916) - Zynq-7000 SoC Silicon Revision Differences

This is a third-party errata, this issue will not be fixed.  

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47916 Zynq-7000 AP SoC Devices - Silicon Revision Differences N/A N/A
AR# 63245
Date 05/28/2018
Status Active
Type Design Advisory
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