We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63329

UltraScale Integrated Interlaken Core - 2014.4 - Invalid Reference Clock Distribution when Channels operating above 16.375 Gb/s


(UG578) UltraScale Architecture GTY Transceivers states that Channels operating above 16.375 Gb/s cannot source a reference clock from another Quad and must use one of the two local reference clock pin pairs in its own Quad.

However, when generating the Interlaken core in 2014.4 and earlier,  one reference clock pin pair (gt_ref_clk_p/n) drives more than one quad at rates above 16.275Gb/s.


This issue was fixed in the 2014.4.1 release.
AR# 63329
Date 03/06/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4
Page Bookmarked