AR# 6334

SYNPLIFY: How to apply the BUFG attribute for XC9500 devices?

Description

Keywords: 9500, Synplify, Verilog, VHDL, BUFG

Urgency: Standard

Genaral Description:
How to apply the BUFG attribute for XC9500 devices within Synplify?

The BUFG attribute can be applied to any input buffer (IBUF), input pad
net, or internal net that drives a CLK, OE, or SR pin.

When applied to an input buffer or input pad net, th BUFG attribute maps
the tagged signal to a global net. When applied to an internal net, the
tagged signal is brought out to a global device control pin and then routed
to the connected internal control pins via a global net. This routing control
results in a higher speed for the affected control path as well as a reduction
in product term utilization. The cost for the improved performance is a
device input pin. The functional behavior remains unchanged.

The BUFG attribute has the following values: CLK, OE, or SR. Where CLK,
OE, and SR indicate clock, output enable, or set/reset, respectively.

In the A1.5 software, BUFG properties can be applied only to input ports.
This means that users who wish to control bus output enable from logic inside
the CPLD (all 9500 - 9500, 9500XL, 9500XV) will need to pass the signal out
to a device pin and back in before connecting to OE control points.

In A2.1i, the BUFG attribute can be applied directly to internal nets. The fitter
will then automatically route the signal through a "GTS" type (or other specified
type) I/O pin to control the OEs.

Notes:
- Synplicity 5.3 and earlier infers BUFG component for 9500 designs when a clock net has >16 fanouts.
This is fine for external input clock. However, the will not work for internal clock.
To workaround this, you need to do two things:
1. Attached syn_noclock attribute for the internal net to prevent BUFG inference.
2. Attached BUFG=CLK attribute on the internal net.
See VHDL/Verilog example for internal clock below.

- While clock inversion is available in every macrocell for 9500XL devices; in 9500 (non-XL) devices
each clock edge is implemented using one global line. Thus, you will be using two BUFGs when both
edges of a clock are used. For example, if you have two clocks (clka and clkb) in a design and uses
both edges of each clock; you will be using a total of 4 global clocks and the design will not fit
(only 3 global clocks are available in 9500/XL devices).
To disable BUFG insertion to a particular clock, set syn_noclockbuf attribute.

Solution

1

// Verilog

module bufg_ex1 (din, clk, qout);
input [1:0] din;
input clk;
output qout;

reg [1:0] qout_int;

wire node /* synthesis syn_keep=1 xc_props="BUFG=OE" */;

always @(posedge clk)
qout_int = din;

assign node = &qout_int;

assign qout = (node)? qout_int[0] : 1'bz;

endmodule

2

-- VHDL

library IEEE;
use IEEE.std_logic_1164.all;
library synplify;
use synplify.attributes.all;

entity bufg_ex1 is
port (din : in STD_LOGIC_VECTOR(1 downto 0);
clk : in STD_LOGIC;
qout : out STD_LOGIC);
end bufg_ex1;

architecture xilinx of bufg_ex1 is

signal qout_int : STD_LOGIC_VECTOR(1 downto 0);

signal node : STD_LOGIC;
attribute syn_keep of node : signal is true;
attribute xc_props of node : signal is "BUFG=OE";

begin

process (clk)
begin
if rising_edge(clk) then
qout_int <= din;
end if;
end process;

node <= qout_int(1) and qout_int(0);

qout <= qout_int(0) when (node = '1') else 'Z';

end xilinx;

3

-- VHDL example for internal clock with SDC file.
-- SDC file is needed to attach BUFG=CLK attribute to appropriate signal

library IEEE,synplify;
use IEEE.std_logic_1164.all;
use synplify.attributes.all;

entity intbufg is port ( i1 : in std_logic;
clka: in std_logic;
da: in std_logic_vector (17 downto 0);
db: in std_logic_vector (17 downto 0);
qa: out std_logic_vector (17 downto 0);
qb: out std_logic_vector (17 downto 0));
end intbufg;

architecture xilinx of intbufg is

signal clkb : std_logic;

begin
process (clka)
begin
if clka'event and clka = '1' then
qa <= da;
clkb <= i1;
end if;
end process;

process (clkb)
begin
if clkb'event and clkb = '1' then
qb <= db;
end if;
end process;

end xilinx;

#========================
#SDC example
# Note: n:clkb denote that the attribute is to be attached to "net" clkb.
# Without "n:" , the attribute will be attached to FD (the flop) instance.

define_attribute {clkb} syn_noclockbuf {1}
define_attribute {n:clkb} xc_props {BUFG=CLK}

4

// Verilog example for internal clock with SDC file.
// SDC file is needed to attach BUFG=CLK attribute to appropriate signal

module intbufg ( i1 , clka, da, db, qa, qb);
input clka, i1;
input [17:0] da, db;
output [17:0] qa, qb;

reg [17:0] qa, qb;
reg clkb;

always @ (posedge clka)
begin
qa = da;
clkb = i1;
end

always @(posedge clkb)
qb = db;

endmodule

#========================
#SDC example
# Note: n:clkb denote that the attribute is to be attached to "net" clkb.
# Without "n:" , the attribute will be attached to FD (the flop) instance.

define_attribute {clkb} syn_noclockbuf {1}
define_attribute {n:clkb} xc_props {BUFG=CLK}

Was this Answer Record helpful?

AR# 6334
Date	04/24/2007
Status	Archive
Type	General Article

Page Bookmarked