In (PG066), JESD204 v6.0, Table 2-30 contains the register description for the Error Reporting (RX Only) register:
Bit 8 and bit 0 appear to be swapped when compared to the jesd204_0_block.v file.
Which is correct?
The file jesd204_0_block.v is correct.
Table 2-30 in (PG066) should show the following:
Disable Error Reporting using SYNC interface is bit 8.
Link Error Counters enable is bit 0.
This is corrected in v6.1 of the Product Guide, (PG066).