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AR# 63354

Vivado 2014.4- 7 Series - CCLK CONFIGRATE setting overides EXTMASTERCCLK_EN Divide value when both are explicitly set

Description

If 

a) the BITSTREAM.CONFIG.CONFIGRATE setting for CCLK is set to a value other than 3 (default), 6, or 12 MHz 

and

b) I explicitly set the EMCCLK enable write_bitstream property (BITSTREAM.CONFIG.EXTMASTERCCLK_EN:Disable | Div-1,2,4,8) to a value other than Disable (default),

then the FPGA will use EMCCLK as the configuration clock source, but it will be divided according to the CONFIGRATE setting, rather than the EXTMASTERCCLK_EN div setting.

Solution


This will be corrected in Vivado 2015.1.

A warning will also be issued stating that the CONFIGRATE setting will be ignored, if you explicitly set the ExtMasterCclk setting to a value other than Disable.
AR# 63354
Date Created 01/20/2015
Last Updated 02/16/2015
Status Active
Type General Article
Devices
  • Kintex-7
  • Artix-7
  • Virtex-7
Tools
  • Vivado Design Suite - 2014.4