When running the JESD204 example design simulation, what timescale is used in the associated testbench?
The JESD204 example design testbench uses a timescale of '1ps.
Some frequencies are rounded to ensure that the bit period of the serial data is a whole number of ps.
Changing the timescale might result in inaccurate results, or simulation failure.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 69881 | JESD204 Solution Center - Design Assistant - Simulation | N/A | N/A |
| AR# 63368 | |
|---|---|
| Date | 10/06/2017 |
| Status | Active |
| Type | General Article |
| IP |
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