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AR# 63372

2014.4 Device Model - Inversion incorrectly added to clock path of RAMD32

Description

A case has been seen where an inversion was incorrectly added to the clock path of a RAMD32 LUTRAM.

The problem occurred when the incoming netlist was read and UNISIM Transformation and Retargeting occurred.

This could potentially happen with other LUTRAM cell types as well.

Solution

This problem has been fixed for the 2015.1 release of Vivado Design Suite.

In the meantime a tactical patch is available for both 2014.4 and 2014.4.1.

The attached patch files can be installed using the following instructions:

Create a separate directory that will contain patch files:
 
1) Extract the contents of the .zip archive to the desired patch directory location.
     
Unzip AR63372_vivado_2014_4_rev1.zip

 
2) Set the MYVIVADO environment variable to point to the patch directory.

Linux:

setenv MYVIVADO /patch/directory/vivado

Windows:

SET MYVIVADO=C:\patch\directory\vivado

 
3) Run Vivado from the original install location.

Note: The correct patch file must be used with 2014.4 and 2014.4.1 respectively.

If not, Vivado will fail to open with the following error message regarding the librdi_netlist library file:
 

ERROR: The file '/proj/xbuilds/2014.4.1_daily_latest/installs/lin64/Vivado/2014.4.1/lib/lnx64.o/librdi_netlist.so' is corrupt. Please re-install this software from the original media.

Attachments

Associated Attachments

Name File Size File Type
AR63372_vivado_2014_4_rev1.zip 4 MB ZIP
AR63372_vivado_2014_4_1_rev1.zip 4 MB ZIP
AR# 63372
Date Created 01/21/2015
Last Updated 03/04/2015
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2014.4