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AR# 63381: Important Embedded IP AXI4 slave interface handshake consideration
Important Embedded IP AXI4 slave interface handshake consideration
On a WRITE transaction, Xilinx embedded IP slave interfaces DO NOT assert the READY signal until the master has driven valid address and control information, AND data on the address and data channel.
The ARM AXI specification describe the AXI protocol channel handshake mechanism in great length.
In summary, A master/slave handshake process is as follows:
All five AXI channels use the VALID/READY handshake to transfer data and protocol information.
The master generates the VALID signal to indicate that address, data or control information is available while the slave generates the READY signal to indicate that it accepts the address, data or control information.
Transfers occur only when both the VALID and READY signals are high.
The slave can wait for AWVALID or WVALID, or both, before asserting AWREADY and WREADY.
As illustrated below, During a WRITE transaction, Xilinx embedded AXI slaves wait for AWVALID and WVALID before asserting AWREADY and WREADY.
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