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AR# 63399

2014.x Vivado IP Packager - Port type "Buffer" not handled as a top level port in VHDL when packaging a custom IP


When using the "BUFFER" port type in the top level VHDL file and packaging the RTL as a custom IP core in the Vivado IP Packager, the "BUFFER" port type will not be included in the port list for the packaged IP.

Example of top level entity definition:


When the Packager is opened using "Tools" --> "Create and Package IP..." it shows all ports except the "s_axis_tready" and "m_axis_tvalid" from the port list as these are "BUFFER" port types.



Is port type of "BUFFER" supported in the Vivado IP Packager?

Is there a workaround?





The "BUFFER" port type is not supported in Vivado IP Packager as of the 2014.4 release.

However, the tools should handle this better and create a Critical Warning for the customer to draw their attention to the port list being incomplete in the packaged IP.

This is planned to be fixed in a future release.

The work-around is to modify the top level entity to use "OUT" port types instead of "BUFFER".


AR# 63399
Date 02/13/2015
Status Active
Type General Article
  • Vivado Design Suite
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