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AR# 63411

2014.4 Vivado UltraScale- Valid LOC constraints on RX/TX ports of GT do not result in correct GT placement


I have a design containing GTs which is targeting UltraScale device.

If only the RX/TX ports of the GTs are LOC constrained, the GTs are not placed correctly.


This issue has been fixed for Vivado 2015.1 which is currently scheduled for release in April 2015. 

The work-around for this issue in Vivado 2014.4 is to LOC constrain the GT directly, as well as the RX/TX ports.

AR# 63411
Date 01/27/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2014.4
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