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AR# 63462

MIG UltraScale - Sample CSV data file for creating Custom Parts

Description

Attached are sample CSV files that can be imported into the MIG UltraScale customization GUI when creating a custom memory part.

Solution

After the CSV file has been imported, the custom memory part must be selected from the drop-down list in the MIG GUI to be used.

The user is responsible for ensuring that all memory parameter values (i.e. CL, CWL, Min/Max Period) and units (i.e. ps, ns etc.) are valid and entered correctly.

If a value is incorrect then you might not see the part listed in the drop-down list, or you might see hardware failures as a result of running an invalid or unsupported configuration.

For example, Only "Components", "UDIMMs", "RDIMMs", "SODIMMs", "LRDIMMs" are acceptable values for Part Type.

DDR4 parts have the following valid ranges and limitations:

  • Rank is limited to 1, 2, and 4 for LRDIMMs, and 1, 2 for all other devices
  • CA Mirror is limited to "0" to disable or "1" to enable address mirroring.
    Note: CA Mirror can only be enabled for Dual Rank devices.
  • Data mask is limited to "0" to disable or "1" to enable data mask.
    Note: Data mask cannot be enabled for x4 devices.
  • Address width is limited to 17 for x8/x16 devices and 18 for x4 devices.
  • Row width is limited to 14, 15, 16, 17, or 18.
  • Column width is limited to 10.
  • Bank width is limited to 2. (Listed as "Bank address in a bank group" for Micron parts).
  • Bank Group width is limited to 1 for x16 devices and 2 for x4/x8 devices. (Listed as "Bank group address" in Micron parts).
  • CS width is limited to 1, and 2.
  • CKE width is limited to 1 and 2.
  • ODT width is limited to 1 and 2.
  • CK width is limited to 1 and 2.
  • Memory Speed grade is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the MIG IP.
  • Memory density is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the MIG IP.
  • Component density is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the MIG IP.
  • Memory device width is limited to 4, 8, and 16 for components and 64, 72 for DIMMs.
  • Memory component width is limited to 4, 8, and 16.
  • Data bits per strobe is limited to 4, and 8.
  • I/O Voltage is limited to 1.2V.
  • Data width is limited to 8,16,24,32,40,48,56,64,72,80.
    Note: Limited to a maximum of 9 components.
  • Min period is limited down to 625ps.
    Note: The minimum speed period is limited based on the FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Max period is limited up to 1600ps.
    Note: The maximum speed period is limited based on the FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • tCKE is limited to 5000ps.
  • tFAW is limited to 10000-35000ps.
  • tMRD is limited to 8-10tck.
  • tRAS is limited to 32000-35000ps.
  • tRCD is limited to12500-15000ps.
  • tREFI is limited to 3900000-7800000ps.
  • tRFC is limited to 90000-550000ps.
  • tRP is limited to 12500-15000ps.
  • tRRD_S is limited to 2500-6000ps.
  • tRRD_L is limited to 4900-7500ps.
  • tRTP is limited to 7500ps.
  • tWR is limited to 15000ps.
  • tWTR_S is limited to 2500ps.
  • tWTR_L is limited to 7500ps.
  • tXPR is limited to 100-560ns.
  • tZQCS is limited to 128tck.
  • tZQINIT is limited to 1024tck.
    Note: Make sure that all DRAM timing parameters values include the proper units and syntax.
    Refer to the attached *.csv file for a reference.
  • CAS Latency is limited to 9 to 24 but specific values can be obtained from the memory vendor data sheet.
    Note: The values often have a range that varies with frequency.
    It is critical that these are entered correctly based on the target memory frequency desired.
  • CAS Write Latency is limited to 9 to 20 but specific values can be obtained from the memory vendor data sheet.
    Note: The values often have a range that varies with frequency. It is critical these are entered correctly based on the target memory frequency desired.
  • Burst Length is limited to 8.
  • RTT (nominal) - ODT is limited to RZQ/6.
  • Stack Height is limited to 1, 2, and 4 (RIDIMMs only).
    Note: This parameter is only used for 3DS parts and should be set to '1' when using non-3DS parts.
  • tFAW_dllr is limited to 16 tck.
    Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
  • tRFC_dlr is limited to 90000-120000 ps.
    Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
  • tRRD_dlr is limited to 4 tck.
    Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
  • tCCD_3ds is limited to 4-5 tck.
    Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.

DDR3 parts have the following valid ranges and limitations:

  • Rank is limited to 1, 2, and 4.
  • CA Mirror is limited to "0" to disable or "1" to enable address mirroring.
    Note: CA Mirror can only be enabled for Dual and Quad Rank devices.
  • Data mask is limited to "0" to disable or "1" to enable data mask.
    Note: Data mask cannot be enabled for x4 devices.
  • Address width is limited to 12, 13, 14, 15, 16.
  • Row width is limited to 12, 13, 14, 15, 16.
  • Column width is limited to 10, 11, 12.
  • Bank width is limited to 3.
  • CS width is limited to 1, 2, and 4.
  • CKE width is limited to 1 and 2.
  • ODT width is limited to 1 and 2.
  • CK width is limited to 1 and 2.
  • Memory Speed grade is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the MIG IP.
  • Memory density is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the MIG IP.
  • Component density is limited to the value defined in the memory vendor data sheet.
    Note: This value is for information purposes only and is not used by the MIG IP.
  • Memory device width is limited to 4, 8, and 16 for components and 64, 72 for DIMMs.
  • Memory component width is limited to 4, 8, and 16.
  • Data bits per strobe is limited to 4, and 8.
  • I/O Voltage is limited to 1.35V and 1.5V.
    Note: Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for maximum supported data rates for 1.35V (DDR3L devices).
  • Data width is limited to 8,16,24,32,40,48,56,64,72,80.
    Note: Limited to a maximum of 9 components.
  • Min period is limited up to 938ps.
  • Note: The minimum speed period is limited based on the FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Max period is limited up to 3300ps.
    Note: The maximum speed period is limited based on the FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • tCKE is limited to 5000-20000ps.
  • tFAW is limited to 25000-55000ps.
  • tMRD is limited to 4tck.
  • tRAS is limited to 33000-37500ps.
  • tRCD is limited to 10000-15000ps.
  • tREFI is limited to 3900000-7800000ps.
  • tRFC is limited to 90000-350000ps.
  • tRP is limited to 10000-15000ps.
  • tRRD is limited to 5000-20000ps.
  • tRTP is limited to 75000-20000ps.
  • tWR is limited to 15000ps.
  • tWTR is limited to 7500-20000ps.
  • tXPR is limited to 100-360ns.
  • tZQCS is limited to 80ns.
  • tZQINIT is limited to 640ns.
    Note: Make sure that all DRAM timing parameters values include the proper units and syntax.
    Refer to the attached *.csv file for a reference.
  • CAS Latency is limited to 5 to 14 but specific values can be obtained from the memory vendor data sheet.
    Note: The values often have a range that varies with frequency.
    It is critical that these are entered correctly based on the target memory frequency desired.
  • CAS Write Latency is limited to 5 to 10, but specific values can be obtained from the memory vendor data sheet.
    Note: The values often have a range that varies with frequency.
    It is critical that these are entered correctly based on the target memory frequency desired.
  • Burst Length is limited to 8.
  • RTT (nominal) - ODT is limited to RZQ/6.

RLDRAM3 parts have the following valid ranges and limitations:

  • Data mask is limited to "0" to disable or "1" to enable data mask.
  • Row width is limited to 20 and 21.
  • Bank width is limited to 4.
  • CS width is limited to 1.
  • CK width is limited to 1.
  • Memory Speed grade is limited to 093, 093E, 125, 125E, 125F, 107, 107E.
  • Memory density is limited to 576Mb, and 1.125Gb.
  • Memory device width is limited to 18 and 36.
  • Data bits per strobe is limited to 9.
  • I/O Voltages are limited to 1.2V.
  • Data widths are limited to 18,and 36 for x18 devices and 36 and 72 for x36 devices.
  • Min period is limited up to 833ps.
    Note: The minimum period is limited based on the FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Max period is limited up to 1250ps.
    Note: The maximum period is limited based on the FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Burst length is limited to 2, 4, and 8.
    Note: Burst Length 8 is not valid when using x36 parts.

QDRII+ parts have the following valid ranges and limitations:

  • Memory Read Latency is limited to 2.0 and 2.5.
    Note: A Read Latency of 2.0 must include the 0 decimal as a value of "2" only will fail to import properly.
  • Burst Length is limited to 2 and 4.
    Note: The Max Period is limited based on Burst Length.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Address Width is limited to 17 thru 23.
  • Memory Speed Grade is limited to 303-633MHz.
  • Memory density is limited up to 576Mb.
    Note: The density should match the address width.
  • Memory device width is limited to 18 and 36.
  • Data bits per strobe is limited to 18 and 36.
  • I/O Voltage is limited to only "1.5V".
  • Data widths limited to "18,36" for x18 devices and "36" for x36 devices.
  • Minimum period is limited up to 1580.
    Note: The minimum period is limited based on FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Maximum period is limited up to 3333.
    Note: The maximum period is limited based on FPGA Package, speed grade and memory configuration.
    Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Only Cypress parts are supported.
  • Cascaded data width is not supported for BL2 parts.
  • BL2 x18 part supports 18 bit data width only.
  • BL2 x36 part supports 36 bit data width only.


QDRIV parts have the following valid ranges and limitations:

  • Performance type is limited to XP or HP.
    Note: The Max Period is limited based on Performance type. Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Memory Read Latency is limited to 8, 5, and 3. 8 and 5 for XP parts and 5 and 3 for HP parts.
  • Burst Length is limited to 2.
  • Address Width is limited from 20 to 23.
  • Memory Speed Grade is limited to 300-1066MHz .
  • Memory density is limited up to 288Mb.
    Note: The density should match the address width.
  • Memory device width is limited to 18 and 36.
  • Data bits per strobe is limited to 9 and 18.
  • I/O Voltage is limited to only "1.2V".
  • Data widths limited to "18" for x18 devices and "36" for x36 devices.
  • Minimum period is limited up to 938 ps.
    Note: The minimum period is limited based on FPGA Package, speed grade and memory configuration. Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Maximum period is limited up to 3333 ps.
    Note: The maximum period is limited based on FPGA Package, speed grade and memory configuration. Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
  • Only Cypress parts are supported.
  • Cascaded data width is not supported for BL2 parts.
  • BL2 x18 part supports 18 bit data width only.
  • BL2 x36 part supports 36 bit data width only.

Note1: Using different OS language types can result in unintended characters being inserted into the CSV file which can prevent the custom part being imported into the MIG part list.

Note2: If you want to verify your values in the generated RTL, be aware that the RTLs units are clock cycles (tck).

Revision History:

03/01/2016Updated for 2015.4 and 2016.1
08/13/2015Updated for 2015.3
05/29/2015Updated CSV files to include additional examples
05/27/2015Updated with valid ranges and limitations
04/15/2015Initial Release

Attachments

Associated Attachments

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
64071 MIG UltraScale - custom memory parts fail simulation N/A N/A
AR# 63462
Date Created 01/29/2015
Last Updated 09/26/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale