UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63494

2014.x Vivado IP Flows - When using a pre-generated IP in my larger project the IP core is reported as out-of-date and forces regeneration, why?

Description

I have a managed IP project which includes all of the necessary IPs for my design. 

I add these IPs as remote sources, keeping them at the managed IP location where the IP is already generated. 

I expect these IPs to be used in my end project without needing to be regenerated.

 

However, they all go out-of-date and regeneration is forced when "Run Synthesis" is selected for the overall project.

Why does this occur?

Is this expected behavior?

 

Solution

This can occur when the original Manage IP project and the later target project do not have the same language setting.

For example, if the Manage IP project is Verilog but the target project is VHDL, Vivado will force the regeneration.

This is the intended behavior.

To avoid the regeneration, the following options are available:

  • Lock the IP in the target project.
  • Ensure both project have the same language setting.
  • Make the MIG core is managed by the user, (i.e. IS_MANAGED property set to 0 for the MIG core)
  • Make the XCI file read only.

 

This expected behavior is also under review at this time and might change in the future to be less restrictive.

 

AR# 63494
Date Created 02/04/2015
Last Updated 03/02/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1