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AR# 63548

2014.4 - IP Integrator - Vivado is erroneously setting the TRACE Port in PS7_INIT.c file without the TRACE being enabled

Description

In my Zynq design, if I generate the output products and investigate the resulting ps7_init.c. Here,  I can see the TRACE ports writes seen below. However, the TRACE port is not enabled and this

may lead to issues during boot stage of the FSBL.

 

EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0xC5ACCE55U),
    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
    // .. .. START: TRACE CURRENT PORT SIZE
    // .. .. a = 2
    // .. .. ==> 0XF8803004[31:0] = 0x00000002U
    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000002U
    // .. ..
    EMIT_MASKWRITE(0XF8803004, 0xFFFFFFFFU ,0x00000002U),
    // .. .. FINISH: TRACE CURRENT PORT SIZE
    // .. .. START: TRACE LOCK ACCESS REGISTER
    // .. .. a = 0X0
    // .. .. ==> 0XF8803FB0[31:0] = 0x00000000U
    // .. ..     ==> MASK : 0xFFFFFFFFU    VAL : 0x00000000U
    // .. ..
    EMIT_MASKWRITE(0XF8803FB0, 0xFFFFFFFFU ,0x00000000U),
    // .. .. FINISH: TRACE LOCK ACCESS REGISTER
    // .. FINISH: TPIU WIDTH IN CASE OF EMIO
    // .. START: QSPI REGISTERS
    // .. Holdb_dr = 1
    // .. ==> 0XE000D000[19:19] = 0x00000001U
    // ..     ==> MASK : 0x00080000U    VAL : 0x00080000U
    // ..

 

How can this be addressed?

Solution

This is a known issue in 2014.4. There is a patch attached to this Answer Record. Please download the patch locally and follow the instructions here on how to use the MYVIVADO patch flow.

Attachments

Associated Attachments

Name File Size File Type
ar63548_Patch.zip 1 MB ZIP
AR# 63548
Date Created 02/11/2015
Last Updated 02/11/2015
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • Vivado Design Suite - 2014.4
IP
  • Processing System 7