I have some XCI files which I have saved in revision control.
When I read, (read_ip) these IPs into memory, (non-project flow) and then try to generate them using the "generate_target" command, I notice my VHDL IP cores are being generated as Verilog cores.
See the following script example:
In my original XCI file which was read into the project, the PREFHDL setting was VHDL:
But after running the IP generation, it then changes to Verilog:
This causes issues with the constraints for my project as instance names no longer match.
Is this expected behavior, and is it possible to ensure that VHDL is maintained?
This is expected behavior. When a project is created, the user should specify the target language. Vivado will follow the user language setting.
To resolve, add the following command into the script prior to generating the IPs.
This command is at the project level and works for all IPs:
So the above script becomes: