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AR# 63576

2014.4 Zynq-7000 FSBL: After booting with PLL Bypassed (MIO[6]=1) the FSBL doesn't enable the PLL


When booting with PLL Bypassed (MIO[6]=1) I expect the FSBL to enable the PLLs (in ps7_init.c) and to use Zynq with the normal clock settings (meaning clock settings with PLL enabled as configured in Vivado).

This is not occurring.


In order to achieve this a modification to the ps7_init.c file is required.

For example, for the standard ZC702 settings, these 3 lines (related to ARM, IO and DDR PLLs) need to be replaced.

    EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), // PLL_BYPASS_FORCE = 1
    EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), // PLL_BYPASS_FORCE = 1
    EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), // PLL_BYPASS_FORCE = 1


In order for PLL_BYPASS_FORCE to control the PLL, PLL_BYPASS_QUAL needs to be 0.

    EMIT_MASKWRITE(0XF8000100, 0x00000018U ,0x00000010U), // PLL_BYPASS_FORCE = 1, PLL_BYPASS_QUAL = 0
    EMIT_MASKWRITE(0XF8000104, 0x00000018U ,0x00000010U), // PLL_BYPASS_FORCE = 1, PLL_BYPASS_QUAL = 0
    EMIT_MASKWRITE(0XF8000108, 0x00000018U ,0x00000010U), // PLL_BYPASS_FORCE = 1, PLL_BYPASS_QUAL = 0


A fix is schedule for the 2015.2 release. 


AR# 63576
Date 03/10/2015
Status Active
Type General Article
  • Zynq-7000
  • Vivado Design Suite - 2014.4