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AR# 63590

7 Series GT Wizard, 2014.4 or earlier - Update to GTZ reset sequence implementation

Description

With the 7 Series GT Wizard in Vivado 2014.4 (or) earlier, the reset sequence is implemented using broadcast read/write addresses to make all GTZ transceivers in the design complete initialization simultaneously.

As recommended in (Xilinx Answer 59038), the reset sequence to the lanes must be staggered to be reset only one lane at a time.

Also, the addresses used for CTLE tuning needs to be corrected.

Solution

This is a known issue with the 7 Series GT Wizard in VIVADO 2014.4 (or) earlier.

To fix this issue, install the patch attached at the end of this answer record and regenerate the core.

This will ensure that the CTLE tuning is done sequentially.

Installation instructions are available in the readme file that is attached.

CTLE tuning is done sequentially with the GTZ transceiver wizard release with VIVADO 2015.1.

Staggering of resets to individual transceivers will be done in VIVADO 2015.2.

To stagger resets in a design generated from 2015.1 (or) with the patch from this AR, please follow the instructions below.

  • Create independent signals to drive RESET input to each instance of the "<component_name>_pll_gtz_tx_rx_ctle" module.
    This instantiation can be found in the <component_name>_init.v file.

  • Release these reset inputs in a staggered manner.
    While doing this, you must ensure that the reset to the master lane (source of tx/rxusrclks) is released first.


Example: A design has 8-lanes (GTZ) and lane0 is sourcing RXUSRCLKs.

  • CTLE tuning is always performed starting on the lane which is the source for RXUSRCLKs.
    CTLE tuning for the remaining transceivers will start sequentially after this.
  • The first initialization of all lanes will always be sequential.

  • If any lane other than lane0 needs to be re-initialized independently, the lane_select_in port can be used to do the re-initialization.
    If lane0 is re-initialized, all of the other lanes needs to be re-initialized again.

Revision History:

2/23/2015 - Initial Release.

5/5/2015 - Updated with more specific details regarding reset and CTLE tuning

Attachments

Associated Attachments

Name File Size File Type
AR63590_GTwizard_v3_4Rev1_preliminary_rev1.zip 17 KB ZIP
AR# 63590
Date Created 02/16/2015
Last Updated 05/27/2015
Status Active
Type General Article
Devices
  • Virtex-7 HT
Tools
  • Vivado Design Suite - 2014.4
IP
  • 7 Series FPGAs Transceivers Wizard