Version Found: v6.1
Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3, See (Xilinx Answer 69037) for RLDRAM3
MIG UltraScale designs might fail with HOLD violations when using the new speed file in 2014.4.1.
Failures can been seen with the following configurations:
DDR3/DDR4 (Data widths >= 64 bits)
RLDRAM3 (All data widths)
If one of the above configurations is being used in 2014.4.1 and HOLD violations are seen within the MIG IP then running "phys_opt_desgin" can resolve the issue.
Post-Place Phys Opt Design (phys_opt_design) can be enabled in the Project Settings under Implementation or can be run manually via the Tcl command "phys_opt_design".
If timing failures are still seen after running "phys_opt_design", check if the violations are the same as the ones identified in (Xilinx Answer 63698).
If not, please open a Service Request for additional assistance.
Revision History:
03/09/2015 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 63175 | Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| 69036 | UltraScale/UltraScale+ DDR3 - Release Notes and Known Issues | N/A | N/A |
| 69037 | UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues | N/A | N/A |
| 69035 | UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 63698 | Design Advisory for UltraScale Kintex FPGA Speed Files - Using ILA cores will show Hold slack violation which can safely be ignored | N/A | N/A |
| AR# 63596 | |
|---|---|
| Date | 12/19/2017 |
| Status | Active |
| Type | Known Issues |
| Devices | |
| IP | |