Version Found: v6.1
MIG UltraScale designs might fail with HOLD violations when using the new speed file in 2014.4.1.
Failures can been seen with the following configurations:
DDR3/DDR4 (Data widths >= 64 bits)
RLDRAM3 (All data widths)
If one of the above configurations is being used in 2014.4.1 and HOLD violations are seen within the MIG IP then running "phys_opt_desgin" can resolve the issue.
Post-Place Phys Opt Design (phys_opt_design) can be enabled in the Project Settings under Implementation or can be run manually via the Tcl command "phys_opt_design".
If timing failures are still seen after running "phys_opt_design", check if the violations are the same as the ones identified in (Xilinx Answer 63698).
If not, please open a Service Request for additional assistance.
03/09/2015 - Initial Release