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AR# 63596

MIG UltraScale - HOLD violations might be seen when using 2014.4.1


Version Found: MIG UltraScale v6.1
Version Resolved: See (Xilinx Answer 58435)

MIG UltraScale designs might fail with HOLD violations when using the new speed file in 2014.4.1.

Failures can been seen with the following configurations:

DDR3/DDR4 ( Data widths >= 64 bits ) 
Speed grade 1 - 1866 Mbps and above designs 
Speed grade 2 - 2133 Mbps and above designs

RLDRAM3 (All data widths  ) 
Speed grade 1 - 1656 Mbps and above designs 
Speed grade 2 - 1800 Mbps and above designs


If one of the above configurations is being used in 2014.4.1 and HOLD violations are seen within the MIG IP then running "phys_opt_desgin" can resolve the issue.

Post-Place Phys Opt Design (phys_opt_design) can be enabled in the Project Settings under Implementation or can be run manually via the Tcl command "phys_opt_design".

If timing failures are still seen after running "phys_opt_design", check if the violations are the same as the ones identified in (Xilinx Answer 63698).

If not, please open a webcase for additional assistance.

Revision History:
03/09/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
63175 Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A

Associated Answer Records

AR# 63596
Date 03/10/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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