Title: CPLL reset sequence
Description: CPLLPD is used to reset the CPLL in UltraScale Transceivers.
In Vivado 2014.4.1 and 2015.1, the CPLLPD pulse generated by the Wizard reset sequence is too short in duration, and this might result in the CPLL not being reset.
Impact: Customers using the following are required to update to 2015.2 Wizard/IPs:
Impacted devices: GTH in Kintex UltraScale production devices, GTH in Virtex UltraScale ES2 devices, GTY in Virtex UltraScale ES1 and ES2 devices.
Impacted IPs: 2014.4.1 Wizard, 2015.1 Wizard and all IPs listed below
Customers using the following are not impacted:
1. GTH in Kintex UltraScale ES1 and ES2 devices and GTH in Virtex UltraScale ES1 devices are not impacted because they use the CPLL calibration block.
To Be Fixed: 2015.2
Status: Resolved in 2015.2 core v1.5 Rev2
Title: Line rate and clock frequency configuration options are not currently limited by the -1L VCCINT=0.90V option.
Description: The Kintex UltraScale Architecture Data Sheet (DS892) specifies that various GTH clock frequency ranges differ between VCCINT=0.90V and VCCINT=0.95V operation for -1L speed grade devices.
This restriction is not enforced by the Wizard.
Work-around: When configuring the Wizard for a -1L speed grade device that you intend to operate at VCCINT=0.90V, consult the relevant Data Sheet for transceiver operational limits.
To Be Fixed: 2015.1
Status: Resolved in 2015.1 core v1.5 Rev1
Title: Receiver termination voltage limited to FLOAT for DC coupled links.
Description: Wizard configurations which use DC link coupling must choose FLOAT for receiver termination.
This selection is available but is not currently enforced by the Wizard.
Work-around: When customizing the Wizard core instance in the GUI, select FLOAT for the Termination field in the Receiver: Advanced section of the first tab.
To Be Fixed: 2015.3
Status: Resolved in 2015.3 core v1.6
Title: GTH CPLL reset disrupts TXOUTCLK in some UltraScale engineering sample devices.
Description: In GTH configurations targeting Kintex UltraScale ES1/ES2 and Virtex UltraScale ES1 engineering sample devices, resetting the CPLL will disrupt the TXOUTCLK signal, even when the CPLL is used for the RX data path and a QPLL is used for the TX data path.
This is due to the presence and operation of the CPLL calibration procedure which briefly takes control of the TXOUTCLK source during CPLL reset, regardless of which resources the CPLL clocks.
Work-around: This behavior cannot be avoided in GTH configurations targeting the affected engineering sample devices.
If runtime disruption to TXOUTCLK in response to resetting the CPLL is not tolerable in configurations where the CPLL drives only RX resources, ensure that you reset and achieve lock on the CPLL prior to, or separate from bringing up TX resources.
Note: This limitation has been added to the UltraScale FPGAs Transceivers Wizard Product Guide (PG182) v1.6.