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AR# 63634

JESD204 PHY v1.0 - TX_RESET_GT and RX_RESET_GT affect both Tx and Rx SERDES for 7 Series FPGA

Description

When generating the JESD204 PHY core v1.0, for 7 Series, the tx_reset_gt affects both the TX and RX SERDES.

The same is true for rx_reset_gt.

In the JESD204B_block.v file, both tx_reset_gt and rx_reset_gt drive the rst_in signal which gives a soft reset to both the TX FSM and the RX FSM.

Is this interaction correct?

Solution

This interaction is incorrect.

The JESD204 PHY core should have separate reset inputs for the RX and TX directions; tx_reset_gt connected to the JESD204 Transmit core, and rx_reset_gt connected to the JESD204 Receive core.

This has been fixed in the JESD204 PHY core v2.0.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61911 LogiCORE IP JESD204 PHY core - Release Notes and Known Issues N/A N/A
AR# 63634
Date Created 02/19/2015
Last Updated 06/10/2015
Status Active
Type General Article
IP
  • JESD204