Issue: TXRESETDONE is LOW but RXRESETDONE is HIGH
If you observe the following behavior, please check the solution mentioned below.
1. TXBUFSTATUS shows overflow/underflow when TXRESETDONE is getting de-asserted.
2. Issue occurs only after programming the FPGA. Applying GTTXRESET after this will resolve the issue.
3. Issue occurs only in slave serial configuration mode. In JTAG mode, the issue does not occur.
4. Issue occurs when RXPLL is shared for both the TX and the RX path. If TXPLL is enabled, the issue does not occur.
5. Issue occurs whether USERCLKs are generated using the GT reference clock (or) TXOUTCLKPMA_DIV2 as the source for TXOUTCLK.
Check if the capacitor used with the reference clock is higher than the recommended 10nF value.
02/19/2015 - Initial Release