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AR# 63640

MIG 7 Series - user must manually add create_clock constraints for sys_clk and ref_clk when "No Buffer" option is chosen

Description

Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)

When a MIG 7 Series IP core is generated with the "No Buffer" option selected, no create_clock timing constraints are added to the MIG IP XDC constraints file. 

Solution

When the "No Buffer" option is selected, you must add create_clock constraints for sys_clk and ref_clk in their top-level XDC to ensure that the timing is properly analyzed.

Revision History:
02/19/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54025 MIG 7 Series - IP Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 63640
Date Created 02/19/2015
Last Updated 02/20/2015
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Artix-7
  • Virtex-7
IP
  • MIG 7 Series