Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)
When a MIG 7 Series IP core is generated with the "No Buffer" option selected, no create_clock timing constraints are added to the MIG IP XDC constraints file.
When the "No Buffer" option is selected, you must add create_clock constraints for sys_clk and ref_clk in their top-level XDC to ensure that the timing is properly analyzed.
02/19/2015 - Initial Release
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