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AR# 63658

2014.4 Partial Reconfiguration - Placer fails to consider the effect of Partpin when placing the cells of the boundary path through the Partition Pin


In a partial reconfiguration design, there is a boundary path from the register in the static logic to the register in the reconfigurable module.

Before the placement of the 2nd configuration, the register in the static logic and the Partpin are placed.



The green diamond in the device view is the source register in the static logic and the yellow diamond is the Partpin.

The entire timing path is as follows: 

From LOCed static register -> LOCed Partpin (far away from the boundary) -> Destination register in RM


To shorten the delay of this path and achieve timing, the destination register should be placed close to the Partpin.

However in the 2nd configuration, the placer places the destination register close to the source register, instead of the Partpin.

As a result it is impossible to get timing closure with the router.


The red diamond in the device view is the destination register.

How can I resolve this issue?


In 2015.1, the destination register will be placed close to the Partpin, which can greatly reduce the path delay.

As a work-around in 2014.4, you will need to do one of the following:

  • Manually fix the destination register to a location close to the Partpin
  • Set the HD.PARTPIN_RANGE property to have the Partpin be placed close to the boundary of the reconfigurable Partition. 
AR# 63658
Date 03/02/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2014.4
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