Version Found: DDR4 v7.0
Version Resolved: See (Xilinx Answer 69035)
When simulating a MIG UltraScale DDR4 design targeted for tCK=833ps, speed bin=833, and using a Micron memory model, the following error message might be seen:
This violation is seen because of an issue with the Micron memory model using the wrong speed bin parameters.
Please contact Micron for a solution and timeline for when this issue will be fixed.
04/01/2015 - Initial Release