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AR# 63684

2014.4 Vivado UltraScale Timing - Min Pulse-width violation on SDR I/O register


I have a min pulse-width violation on an SDR I/O register.

What options do I have to get around this violation?


The SDR register in the UltraScale and UltraScale+ has a lower Fmax than in previous families.

If you require a higher frequency than is possible in the SDR register then you have the following options to fix this violation:

  1. Convert the BITSLICE flip-flop to the IDDR/ODDR element.

    • If using an input SDR, use an IDDR and only monitor one of the Q outputs. You will need to tell the timing tools not to analysis for both clock edges. Below is an example constraint.
      Note: this will be applied globally to the clock.

set_false_path -setup -rise_from [get_clocks <<clock_name>>] ] -fall_to [get_clocks  <<clock_name>>] ]
set_false_path -setup -fall_from [get_clocks <<clock_name>>] ] -rise_to [get_clocks <<clock_name>>] ]

set_false_path -hold -rise_from [get_clocks <<clock_name>>] ]  -rise_to [get_clocks <<clock_name>>] ]
set_false_path -hold -fall_from [get_clocks <<clock_name>>] ]  -fall_to [get_clocks <<clock_name>>] ]

    • If using an output SDR, use an ODDR and connect the same signal to both D1 and D2. You will need to tell the timing tools that there is a multicycle path for the ODDR inputs:

set_multicycle_path -from [get_clocks <<clock_name>>] -to [get_ports <<output_port>>] 2
set_multicycle_path -from [get_clocks <<clock_name>>] -to [get_ports <<output_port>>] -hold 2

  1. Migrate the register from the BITSLICE site into the SLICE flip-flop (IOB = FALSE).

    • To ensure the register is not placed in the IOB, use the following XDC constraint:
set_property IOB FALSE [get_cells <<inst_name>>]
AR# 63684
Date 07/29/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale