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AR# 63689

MIG UltraScale QDRII+ - Read Latency 2.0 (RL2) and Burst Length 2 (BL2) designs fail simulation with Cypress memory model


Version Found: MIG UltraScale v7.0
Version Resolved: See (Xilinx Answer 58435)

For MIG UltraScale QDRII+ designs configured for Read Latency 2.0 (RL2) and Burst Length 2 (BL2), IES and VCS simulations can fail with data mismatch error messages coming from the Cypress memory model.


This is a known issue with the CY7C2644KV18 and CY7C2542KV18 Cypress memory models.

Please contact Cypress directly to resolve this issue with their models.

Revision History:
02/24/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 DDR4, DDR3, QDRIV, QDRII+, RLDRAM3, LPDDR3 UltraScale and UltraScale+ - IP Release Notes and Known Issues N/A N/A
AR# 63689
Date 04/30/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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