AR# 63698


Design Advisory for UltraScale Kintex FPGA Speed Files - Using ILA cores will show Hold slack violation which can safely be ignored


The UltraScale Kintex FPGA Speed Files (rev 1.13) will show a Hold slack violation on a dedicated connection used in the ILA core. 

The speed files are overly pessimistic on some slice pin timing requirements, which results in timing violations on purely dedicated paths. 

These paths will not fail when designs are run in hardware. 

Specifically, the primitives used are CFGLUT5s, which are not inferred by synthesis tools, but are only used by the ILA core. 
As a result, the timing violations that result when ILA cores are instantiated can be safely ignored.

In the below example, the violation can be seen as a 9 ps violation, and this value may shift slightly depending on which dedicated pins are used for the connection.
Slack (VIOLATED) :        -0.009ns  (arrival time - required time)
  Source:                 ILA_inst/inst/<path>/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlC/S1/CLK
  Destination:          ILA_inst/inst/<path>/I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE/u_srlB/S2/D


The speed files are scheduled to be updated with the correct hold time values in 2015.1.

The datasheet will reflect the new speed file version of 1.15 for Production devices when 2015.1 is released.   


For designs run using Vivado 2014.4.1 with the Production rev 1.13, the Hold slack violations for the ILA_inst core from CLK to D can be safely ignored, and these timing violations will not cause hardware failures.

Revision History:
1.1 - Initial release of information

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
63596 UltraScale DDR4/DDR3/RLDRAM3 - HOLD violations might be seen when using 2014.4.1 N/A N/A
AR# 63698
Date 05/12/2015
Status Active
Type Design Advisory
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