AR# 63700

LogiCORE IP Video Timing Controller v6.1 - Driver does not set 'Interlaced' bit in Generator Encoding Register


I am having trouble getting the VTC to generate interlaced signals when using the driver.

What can cause this?


The video timing controller has a runtime option to be programmed in either progressive or interlaced mode.

However, the driver (XVtc_SetGenerator) never sets the generator encoding register (Address offset 0x0068) to switch between progressive and interlaced.

This will be fixed in the next version of the driver.

In the meantime, you can work around this by manually setting this bit via a register write in user code.
AR# 63700
Date 03/16/2015
Status Active
Type General Article