UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63716

Kintex UltraScale FPGA HR I/O Transition at the End of Startup

Description

In Kintex UltraScale devices which have the multi-function configuration pins on HR I/O banks, if the VCCO for the bank is 1.8V or lower, and if a pin on that bank is Low or floating, then the input might have a 0-1-0 transition to the interconnect logic during configuration startup.

Because this transition occurs after GWE enables the internal logic, it might affect the internal state of the device after configuration.

Note that this applies not only to the multi-function configuration bank 65, but also bank 70 in the Kintex UltraScale devices based on SSI technology.

In the Kintex UltraScale FPGA, this transition can occur approximately one CFGCLK after EOS (End Of Startup).
 
No action is required for logic that is not impacted by input transitions during startup, for example logic that does not register inputs during startup or that is reset through/after startup.
 
Affected Implementations:
The affected Kintex UltraScale devices and HR I/O banks are shown in Table 1:
 

63716-1.png




A Kintex UltraScale FPGA design can be affected when ALL of the following are TRUE:
  •  
    • Device = Kintex UltraScale device
    • VCCO_0 = 3.3V or 2.5V (i.e. when CFGBVS=VCCO_0)
    • VCCO_65 = 1.8V or lower (or when available VCCO_70 = 1.8V or lower)
    • Bank 65 is a HR I/O bank (or when available bank 70 is a HR I/O bank)
    • The input pin state is Low or floating during configuration startup
    • User design is impacted by a 0-1-0 input transition during configuration startup
Impact:

When ALL of the above are TRUE, the internal signal from an input pin in bank 65 (or if applicable, bank 70), might have a 0-1-0 transition approximately one CFGCLK cycle after end of startup (EOS).

This internal input signal transition can affect the state of internal logic.

The internal input signal is clear of the potential transition by 200 nS after EOS.

63716-2.png


Figure 1: HR I/O Bank 65/70 Potential Input Transition Window Following EOS
 
References:
For additional information, see the I/O Transition at the End of Startup section in the UltraScale Architecture Configuration User Guide (UG570).

http://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

Solution

A number of work-arounds are available, including the following:
  • Use the same voltage across VCCO_0 and VCCO_65 (and if applicable bank 70) in the PCB design.
  • Keep affected bank 65 (or if applicable bank 70) input pins at a High state from startup through at least the end of the affected window of time near EOS.
  • Include logic in a synchronous FPGA design that delays the start of the clock(s) to the affected logic until at least the end of the affected window of time following EOS.
  • Include logic in the FPGA design that ignores affected input signals from startup through at least the end of the affected window of time following EOS.
 
For the FPGA design work-arounds, an IGNORE_INP_B signal can be created using an EOS signal from the STARTUPE3 primitive and a suitably long counter or shift register to either delay the clock(s) to the affected logic or gate the affected input signals.

The active-High EOS output signal from the STARTUPE3 primitive signifies the end of configuration startup which begins the affected window of time.

Example block diagrams of potential FPGA design work-arounds are shown in Figure 2 and Figure 3, below:

 

figure2-63716.png




 

Note: Figure 3 is a simplified, conceptual example.

Input gating can be implemented differently to ensure release synchronous to logic clock(s).

AR# 63716
Date Created 02/26/2015
Last Updated 07/13/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale