In Kintex UltraScale devices which have the multi-function configuration pins on HR I/O banks, if the VCCO for the bank is 1.8V or lower, and if a pin on that bank is Low or floating, then the input might have a 0-1-0 transition to the interconnect logic during configuration startup.
Because this transition occurs after GWE enables the internal logic, it might affect the internal state of the device after configuration.
Note that this applies not only to the multi-function configuration bank 65, but also bank 70 in the Kintex UltraScale devices based on SSI technology.
In the Kintex UltraScale FPGA, this transition can occur approximately one CFGCLK after EOS (End Of Startup).
No action is required for logic that is not impacted by input transitions during startup, for example logic that does not register inputs during startup or that is reset through/after startup.
When ALL of the above are TRUE, the internal signal from an input pin in bank 65 (or if applicable, bank 70), might have a 0-1-0 transition approximately one CFGCLK cycle after end of startup (EOS).
This internal input signal transition can affect the state of internal logic.
The internal input signal is clear of the potential transition by 200 nS after EOS.