In addition to this one, affected macros include ADDMACC_MACRO.vhd, ADDSUB_MACRO.vhd, EQ_COMPARE_MACRO.vhd.
The equivalent Verilog UNIMACRO library cells do not have this issue.
To work around the DRC issue, manually modify the following two lines in this file.
CEA1_IN <= CE when (AREG_IN = 1) else '0';
CEB1_IN <= CE when (BREG_IN = 1) else '0';
These two lines should be changed to:
CEA1_IN <= CE when (AREG_IN = 2) else '0';
CEB1_IN <= CE when (BREG_IN = 2) else '0';
To obtain correct simulation results, we recommended that as an alternative, you instantiate the DSP48E primitive in the design.
This problem also exists in the ISE UNIMACRO library components for V5, V6 and 7 series devices.
The ISE UNIMACRO library files are located in <ISE installation directory>\ISE\vhdl\src\unimacro.
The work-around for ISE is the same.
This issue is fixed starting in Vivado 2015.3.