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AR# 63737

2014.4 Partial Reconfiguration - Pushing constant across Partial Reconfiguration (PR) boundary results in incorrect Static logic optimization


My hardware test of a partial reconfiguration design fails in a simple 2 bit register value.

The 2 bit register is in static logic and driven by the VCC/GND net in a reconfigurable module.

Comparing the logic between the pre and post-opt design DCPs reveals that static logic is being removed.
In the schematic of the pre-opt design, you can see the 2 bit register in the static logic.

In the schematic of the post-opt design, the 2 bit register in the static logic is removed.



The issue will be fixed in the 2015.1 release of Vivado.

To work around this issue in Vivado 2014.4, you can set the DONT_TOUCH property on the static logic that is optimized.
AR# 63737
Date 03/04/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2014.4