When Generating a bitfile from a 2014.4 Ethernet 1000BASE-X PCS/PMA or SGMII example design, the following DRC error is received:
How can I avoid this?
The DRC is valid in this case and was added in Vivado 2014.4.
The IDELAYCTRL RST pin must be synchronously deasserted with respect to REFCLK for both 7 Series and UltraScale for proper IDELAY/ODELAY operation.
It is active high.
The 2015.1 Ethernet 1000BASE-X PCS/PMA or SGMII example design has the correct structure.