We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 63770

Vivado - REQP-1817 DRC error with SGMII example design


When Generating a bitfile from a 2014.4 Ethernet 1000BASE-X PCS/PMA or SGMII example design, the following DRC error is received:


ERROR: [Drc 23-20] Rule violation (REQP-1817) IDELAYCTRL_RST_connects_to_CMT_LOCKED_pin - The IDELAYCTRL core_wrapper_i/inst/core_clocking_i/core_idelayctrl_i/core_wrapper_i/inst/core_clocking_i/core_idelayctrl_i/dlyctrl_REPLICATED_0 RST pin is driven by the LOCKED pin of the CMT cell driving the LUT cell core_wrapper_i/inst/core_clocking_i/core_idelayctrl_i/dlyctrl_i_1. The UltraScale IDELAYCTRL requires that the RST signal gets synchronized to the REFCLK domain.


How can I avoid this?


The DRC is valid in this case and was added in Vivado 2014.4. 

The IDELAYCTRL RST pin must be synchronously deasserted with respect to REFCLK for both 7 Series and UltraScale for proper IDELAY/ODELAY operation.

It is active high.

The 2015.1 Ethernet 1000BASE-X PCS/PMA or SGMII example design has the correct structure.

AR# 63770
Date 04/13/2015
Status Active
Type General Article
  • Vivado Design Suite - 2014.4.1
  • Ethernet 1000BASE-X PCS/PMA or SGMII
Page Bookmarked