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AR# 63786

UltraScale DDR4 - SPEC_VIOLATION tWR/tRTP tWR seen for tCK = 833ps and speed bin = 833 when using Micron Memory Model


Version Found:DDR4 v7.0

Version Resolved: See (Xilinx Answer 69035)

When simulating a MIG UltraScale DDR4 design targeted for tCK=833ps, with speed bin=833, and using a Micron memory model, the following error can occur:

ERROR:SPEC_VIOLATION tWR/tRTP tWR spec:19 loaded:16 tRTP spec:7432 loaded:7432 @4205744


This violation is seen because of an issue with the Micron memory model using the wrong speed bin parameters.

Please use the updated Micron Memory model to avoid these issues.

Revision History:

04/01/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69035 UltraScale/UltraScale+ DDR4 - Release Notes and Known Issues N/A N/A
AR# 63786
Date 01/12/2018
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
  • MIG UltraScale
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