Description

Version Found: DDR3 v7.0

Version Resolved: See (Xilinx Answer 69036)

When simulating a MIG UltraScale DDR3 design using a Micron memory model targeting the sg125 speed grade with CAS Latency = 9 and CAS Write latency = 7, the following error message might be received:

# sim_tb_top.mem_model_x8.memRank[0].memModel[2].u_ddr3_x8.main: at time 6947904.0 ps ERROR: CAS Latency =           9 is illegal @tCK(avg) = 1500.220703
# sim_tb_top.mem_model_x8.memRank[0].memModel[2].u_ddr3_x8.main: at time 6947904.0 ps ERROR: CAS Latency =           9 is not valid when CAS Write Latency =           7

Solution

According to the Micron data sheet for the sg125 speed grade, CAS Latency=9 and CAS Write Latency=7 is supported.

Please use the updated Micron Model.

Revision History:

04/01/2015 - Initial Release

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