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AR# 63788

MIG UltraScale DDR3 - tRRD and tFAW errors seen in behavioral simulation


Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 58435)

When simulating a MIG UltraScale DDR3 design, the following error message might be seen:

sim_tb_top.mem_model_x8.memRank[0].memModel[0].u_ddr3_x8.chk_err: at time 7198625.0 ps ERROR: tRRD violation during Activate to bank 2
sim_tb_top.mem_model_x8.memRank[0].memModel[0].u_ddr3_x8.cmd_task: at time 7222625.0 ps ERROR: tFAW violation during Activate to bank 1
sim_tb_top.mem_model_x8.memModel[7].ddr4_model.:ERROR:SPEC_VIOLATION tWR/tRTP tWR spec:19 loaded:16 tRTP spec:7432 loaded:7432 @4205744


These errors are a result of a known limitation on the MMCM/PLL that results in an alternating period of 1ps variance (i.e. 6000ps, 5999ps, 6000ps, and 6001ps).

This issue occurs for a small subset of input and output clock frequency combinations and can be safely ignored.

Revision History:

04/01/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 63788
Date 08/05/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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