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AR# 63817

7 Series FPGAs Transceivers Wizard Example Design v3.5 - Use of clocking resources to check for tx|rxoutclk


The startup FSMs for RX and TX check that tx|rxoutclk is present before releasing the reset of the MMCM. 

This is done through one flip-flop for pmaresetdone which is clocked directly with tx|rxoutclk.


For IP generation reasons there is currently an extra BUFG used that clocks this logic.

As a result, tx|rxoutclk is driving two BUFGs, one for the MMCM input and one for the check logic.
This can result in a shortage of BUFGs in some designs.


If a design runs into congestion errors due to clock routing, or runs out of clocking resources due to this additional BUFG, you can do the following by changing the transceiver core setup:


The output of the BUFG (which is driving the input of the MMCM), can be routed back to the startup FSMs and the additional BUFG in the *_init module can be removed, or vice versa.

AR# 63817
Date 03/09/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Virtex-7Q
  • Kintex-7Q
  • Artix-7Q
  • Less
  • Vivado Design Suite - 2015.1
  • 7 Series FPGAs Transceivers Wizard
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