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AR# 63886

2015.1 Vivado Timing Analysis - CRITICAL WARNING: [DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for...

Description

Version Found: MIG 7 Series v2.0 Rev 3
Version Resolved: See (Xilinx Answer 54025)

In MIG 7 series, for certain combinations of system clock vs. memory operating frequencies, the design can issue critical warnings during implementation or simulation:
 

CRITICAL WARNING: [DRC 23-20] Rule violation (AVAL-46) v7v8_mmcm_fvco_rule1 - The current computed target frequency, FVCO, is out of range for cell u_mig_7series_0/u_mig_7series_0_mig/u_infrastructure/gen_mmcm.mmcm_i. The computed FVCO is 1600.256 MHz The valid FVCO range for speed grade -3 is 600MHz to 1600MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 8.000, CLKIN1_PERIOD = 4.99920, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).

Solution

This error is due to a rounding error in the time period calculations and can be seen in specific configurations.
 

To work around it,  increase or decrease the system clock period by 1ps. 

If the warnings are noticed in simulation, change the system clock time period to +/-1 PS in the top level RTL file. 

For implementation, both the XDC and top level RTL files should be modified. 

 

 
AR# 63886
Date Created 03/12/2015
Last Updated 04/30/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1
IP
  • MIG 7 Series